The present invention generally relates to low-pass filtering of electrical signals, and more particularly to a low-pass filter having an adjustable cut-off frequency.
When an analog signal is sampled, spectral components at frequencies greater than one half the sample rate are overlaid on the components below one half the sample rate. This effect, known as aliasing, can sometimes be exploited as a benefit. However, aliasing is mostly considered detrimental and results in a noisy signal.
Aliasing is typically addressed by interposing a low-pass anti-aliasing filter before the analog-to-digital converter (ADC). If the maximum frequency of interest is fmax and the sample rate is fs, the anti-aliasing filter must have a pass band from DC to fmax, a transition band from fmax to (fsxe2x88x92fmax), and a stop band above (fsxe2x88x92fmax).
Conventional integrated-circuit analog filter design techniques involve building into silicon the components (resistors, capacitors etc.) that define the frequency characteristics of the filter. Thus, once a chip is made, the frequency characteristics of the filter are fixed. This approach limits the range of applications for which a particular device is suitable. For example, if a filter and an ADC are integrated with a field programmable gate array (FPGA) in a device, the pass band, transition band, and stop band are fixed at the time the device is made. However, users will likely desire different frequency bands for different applications. Since all the desired frequency bands are generally unknown at the time the device is made, the device will be suitable for only certain applications.
A circuit arrangement that address the aforementioned problems, as well as other related problems, is therefore desirable.
An anti-aliasing filter with adaptable cutoff frequency is provided in various embodiments of the invention. In one embodiment, the filter includes a calibrator/adaptor section and an anti-aliasing filter section. Both sections include a cascaded arrangement of adjustable delay circuits, and the calibrator/adaptor section includes a control circuit. A reference signal is input to the delay circuits and the control circuit of the calibrator/adaptor section, and an analog input signal is input to the delay circuits of the anti-aliasing filter. The control circuit compares the directly received reference signal to the reference signal from the last delay circuit and generates an adjustment signal responsive to the comparison. The delay intervals of all the delay circuits are adjustable responsive to the adjustment signal from the control circuit. In another embodiment, the anti-aliasing filter is used in an analog-to-digital conversion (ADC) system having a selectable sample clock rate. When the base sample clock rate is a lower frequency, the input analog signal bypasses the anti-aliasing filter and is input to an ADC circuit, which over-samples and digitizes the signal responsive to a multiplied base sample clock rate. The digital data is then decimated for compliance with the base sample rate. When the base sample clock rate has a higher frequency, the input analog signal is input first to the anti-aliasing filter and then to the ADC circuit. The ADC circuit does not over-sample when operating at the higher frequency, and therefore, no decimation of the data is required.
In another embodiment, the anti-aliasing filter is used in a digital-to-analog conversion (DAC) system having a selectable sample clock rate. When the base sample rate of the system is a lower frequency, digital data are interpolated responsive to a multiplied base sample rate. The interpolated data is thereafter converted to an analog signal by a DAC circuit. When the base sample rate is a higher frequency, the digital input is converted to an analog signal, bypassing the interpolation. The anti-aliasing filter is used to implement a reconstruction filter, which filters the analog signal from the DAC circuit.
Various other embodiments are set forth in the Detailed Description and Claims which follow.